The present invention generally relates to computing devices and, more particularly, to systems and methods for cache balance when using hardware transactional memory.
Hardware transactional memory (HTM) is a model for controlling concurrent memory accesses in the scope of parallel programming and is an alternative to lock-based synchronization. Similar to a database transaction, within the scope of a transaction, HTM either commits or discards (e.g., in the event of a conflict) all shared memory accesses and their effects (i.e., all changes inside of the transaction). HTM provides for atomicity (e.g., all speculative memory updates of a transaction are either committed or discarded as a unit), consistency (e.g., memory operations of a transaction take place in order, and transactions are committed one at a time), and isolation (e.g., memory updates are not visible outside of a transaction until the transaction commits data).